1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device which can be applied to a flash memory, for example.
2. Description of the Related Art
FIG. 10 shows a NAND-structured cell using an EEPROM. One NAND is constructed by serially connecting the current paths of a plurality of memory cells MC and connecting first and second selection gates SG1 and SG2 to both ends of the series circuit of memory cells MC. The first selection gates SG1 in the respective NANDs are connected to bit lines BL0, BL1, BL2, respectively, and the second selection gates SG2 are grounded. The control gates of the memory cells of each NAND are respectively connected to word lines WL0, WL1, WL2, --, WLn. The gates of the first selection gates SG1 are connected to a first selection line SL1 and the gates of the second selection gates SG2 are connected to a second selection line SL2.
With the above construction, the operation effected when data stored in the memory cell is read out is explained. First, in a case where data is read out from the memory cell connected to the word line WL2, 0 V is applied to the word line WL2 and a power supply voltage Vcc, for example, 5 V is applied to all of the other word lines, all of the bit lines, and all of the first and second selection lines. The memory cells connected to the non-selected word lines act as transfer gates and data is read out from the cell transistor connected to the selected word line WL2 via the transfer gates. That is, data of "1" or "0" is determined according to whether the cell transistor is set in the ON or OFF state. Therefore, the threshold voltage of the memory cell storing data "1" must be negative and the threshold voltage of the memory cell storing data "0" must be positive. Further, the threshold voltage of the memory cell acting as the transfer gate must be lower than potential Vcc.
On the other hand, when data is written into the memory cell, the data writing operation is effected for each word line. For example, in a case where data is written into the memory cell connected to the word line WL2, 20 V is applied to the word line WL, 10 V is applied to all of the other word lines, 12 V is applied to the first selection line SL1, and 0 V is applied to the second selection line SL2. If the potentials of the bit lines BL0, BL1 and BL2 are respectively set at 0 V, 10 V and 0 V, the potential difference between the channel and the control gate of each of the memory cells MC20 and MC22 is set to 20 V and electrons are injected into the floating gates of the memory cells MC20 and MC22 by F-N (Fowler-Nordheim) tunneling. No tunneling phenomenon occurs in the memory cell MC21 since the potential difference between the channel and the control gate thereof is small and no electrons are injected into the floating gate thereof.
Even when the same voltage is applied to the memory cells, the injection amount of electrons is different in the memory cells and the threshold voltage cannot be set to a constant value. As the cause for a variation in the threshold voltage, it is considered that the ratio of a capacitance between the control gate and the floating gate to a capacitance between the substrate and the floating gate is not constant. Therefore, it is considered that the potential of the floating gate becomes different for each memory cell and the injection amount of electrons becomes different when a high potential is applied to the word line.
In order to cope with the above case, data is read out from the memory cell and verified to check whether the condition of the threshold voltage is satisfied or not when the writing operation is completed. If it is detected that data is not correctly written as the result of verification, the writing operation is repeatedly effected until the lower limit of the threshold voltage of the memory cell into which data "0" is written becomes higher than 0.5 V, for example.
However, in a case where data is written in the above-described manner and if a variation in the threshold voltage of the memory cells is large, the upper limit of the threshold voltage of the memory cell into which data "0" is written sometimes exceeds Vcc when the lower limit of the threshold voltage of the memory cell into which data "0" is written has exceeded 0.5 V. Since the memory cell which is thus excessively written cannot act as the transfer gate at the data readout time, it becomes impossible to read out data of one NAND containing the above memory cell.